1. Field of the Invention
The invention relates to maintaining time synchronous with a network master time. More particularly, the invention concerns generating a clock signal for maintaining synchronism with network time in a primary mode and in a powersaving secondary mode.
2. Description of the Related Art
Code division multiple access (CDMA) cellular radiotelephone networks are a widely used type of spread spectrum communication system. Frequently, mobile telephones are small handheld units operating from battery power. Consequently, power conservation is a constant goal of handheld radiotelephone designers. A well known technique for saving power entails reducing the clock rate, or completely cutting off the clock, supplied to components of the radiotelephone that are not needed for the present mode of operation of the telephone. When the clock to selected components is reduced or eliminated, the telephone is in what is referred to as a secondary mode of operation.
For a CDMA radio telephone system to operate correctly, it is necessary for the radiotelephone to have a master timer that establishes and maintains synchronism with a CDMA network timer. To enable the radiotelephone to resume communications with a base station quickly and without using an excessive amount of power after leaving the secondary mode, the radiotelephone must maintain synchronism with the network timer even when the radiotelephone is in the secondary mode.
Typically, a radiotelephone has an analog transceiver that is commonly left operating when the radiotelephone is in the secondary mode, because the radiotelephone provides timing signals. However, leaving the analog transceiver operating during the secondary mode increases power consumption during the secondary mode due to the power consumption of the analog transceiver.
Consequently, there is a need for a way to maintain CDMA network time in a radiotelephone while the radiotelephone is in the secondary mode, without running the analog transceiver. Additionally, it would be desirable to clock a digital transceiver in a radiotelephone at a frequency higher than the commonly used frequency of chiprate(8), in order to allow for more efficient useage of digital transceiver resources through timesharing.
An illustrative embodiment of the invention is an integrated circuit device having a clock generator. The clock generator has a primary input for coupling to a primary reference frequency source, a secondary input for coupling to a secondary reference frequency source, and an output that produces a primary digital transceiver clock signal having a frequency of chiprate (S)(n) in a primary mode, and that produces a secondiary digital transceiver clock signal having a frequency of chiprate in a secondary power saving mode. Preferably, the primary reference frequency source is a voltage controlled, temperature compensated crystal oscillator (VCTCXO), and the secondary reference frequency source is a crystal/oscillator (meaning that it can be a crystal or an oscillator). The device also includes a chiprate divider having an input that is coupled to the output of the clock generator. An output of the chiprate divider produces a primary mode enable signal that has a frequency of chiprate when in a primary mode. The device also includes a long PN generator and a short PN generator. A clock input of the long PN generator and a clock input of the short PN generator are coupled to the output of the clock generator. The device also includes a first multiplexer that has a first input coupled to the output of the chiprate divider, and a second input coupled to an output providing a secondary mode enable signal, and an output coupled to an enable input of the long PN generator and to an enable input of the short PN generator. The device also includes a controller that has a control output coupled to a control input of the first multiplexer. The controller produces a first control signal at the control output for producing the primary mode enable signal at the output of the first multiplexer in a primary mode, and the controller produces a second control signal at the control output for producing a secondary mode enable signal at the output of the first multiplexer in a secondary mode. The control signal may be a single signal that is used to select between the primary mode and the secondary mode.
The clock generator includes a primary digital transceiver clock generator having an output producing the primary digital transceiver clock signal, and an alternate source divider having an output producing the secondary digital transceiver clock signal. The clock generator also includes a multiplexer having an output that produces the primary digital transceiver clock signal when the multiplexer receives the first control signal from the controller, and that produces the secondary digital transceiver clock signal when the multiplexer receives the second control signal from the controller.
The device also includes a clock calibrator for measuring the frequency difference between 1/(S)(n) times the frequency of the primary digital transceiver clock signal and the frequency of the secondary digital transceiver clock signal as a function of time. The device also includes a secondary mode timer that produces a signal indicating the amount of time that the secondary mode is in effect. The controller has a calibrator input coupled to the output of the clock calibrator, and timer input coupled to the output of the secondary mode timeR. The controller is configured to calculate the cumulative frequency error during the time that the secondary mode is in effect. The controller also includes a master timer adjustment output that produces a signal for advancing or retarding a master timer to reduce the frequency error between the long PN generator and the short PN generator on the one hand, and the CDMA network time on the other hand. The device also includes a master timer having an input coupled to a master timer adjustment output of the controller.
The invention can also be implemented as a radiotelephone and as a method. The invention advantageously provides for generation of a primary digital transceiver clock signal having a frequency that is higher than commonly used digital transceiver clock signals, to allow for more efficient usage of digital transceiver resources through timesharing. The invention also provides for maintaining CDMA network time without operating an analog transceiver during the secondary mode, thereby reducing power consumption during the secondary mode. Additional advantages and benefits of the invention will be apparent from the following description.